Use of thin SOI to inhibit relaxation of SiGe layers

ABSTRACT

High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.

FIELD OF THE INVENTION

The present invention relates to a method of fabricatingSiGe-on-insulator substrate materials, and more particular to a methodof fabricating SiGe-on-insulator substrate materials in which the SiGealloy layer is metastable, yet very resistant to relaxation. The presentinvention also relates to the SiGe-on-insulator substrate materialsproduced using the method of the present invention.

BACKGROUND OF THE INVENTION

In the semiconductor industry, there has recently been a high-level ofactivity using strained Si-based heterostructures to achieve highmobility structures for complementary metal oxide semiconductor (CMOS)applications. In such heterostructures, the strained Si is typicallyformed atop a relaxed SiGe alloy layer.

Relaxation of SiGe alloy layers can occur when the thickness of thelayer exceeds a certain value (called the critical thickness) for agiven Ge concentration in the alloy. The relaxation of strained SiGealloy layers that are thicker than the critical thickness occursprimarily through the formation of strain-relieving misfit dislocations.Strained SiGe layers that are grown thicker than the critical thickness,but remain strained and defect-free, are said to be metastable. In fact,any strained layer whose total film energy (including the strain,thickness and defect components) is not minimized with respect to defectproduction is, by definition, metastable.

Metastable-strained SiGe layers can be defect free if the growthconditions are chosen correctly. Specifically, relaxation by defectformation almost always occurs at local microscopic defect sites at thestrained Si/SiGe interface. The growth of metastable SiGe layers, then,is most successful when the growth surface is atomically clean and freeof existing defects. Once a metastable SiGe layer is grown, it can relaxif the layers are annealed at a high enough temperature. The nucleationand growth rate of misfit dislocations are strongly temperaturedependent. Relaxation occurs by defect production and growth until 1)there is not enough strain energy within the film to create anotherdislocation, and 2) the existing dislocations stall, become pinned, orget trapped by some other mechanism.

The above physical properties of metastable strained SiGe layers putlimitations on what initial SiGe layers can be applied to the thermalmixing method of fabricating SiGe-on-insulator (SGOI) substratematerials. The thermal mixing method is disclosed, for example, inco-pending and co-assigned U.S. patent application Ser. No. 10/055,138,filed Jan. 23, 2002, entitled “Method to Create High-QualitySiGe-On-Insulator for Strained Si CMOS Applications”.

If a thermodynamically stable SiGe layer is grown on asilicon-on-insulator (SOI) substrate and subsequently oxidized at hightemperatures (on the order of about 1200° C. or greater), the final SGOImaterial formed will generally remain fully strained. This is becausethe only mechanism available to relieve strain at the substrate level isthrough defects; and since there is not enough strain energy to formdefects, no relaxation occurs. If a metastable SiGe layer is grown on anSOI substrate and oxidized at high temperatures, the layer will tendtowards a minimum film energy condition with respect to the residualSiGe film strain and the extent of lattice relaxation (by defectgeneration). In some applications, it is advantageous to form SGOI thatremain fully strained, i.e., no relaxation, rather than a relaxed SiGelayer.

In view of the above, it would seem that the fabrication of fullystrained SiGe-on-insulators is only possible by using thermodynamicallystable SiGe layers. Such a method however places constraints on thetotal SGOI film thickness for a given Ge concentration.

Despite the current state of the art, applicants are unaware of anyongoing effort to create a “frustrated” SGOI film in which the SiGelayer is metastable, yet very resistant to relaxation.

SUMMARY OF THE INVENTION

The applicants of the present application have determined that whenhigh-quality, metastable SiGe alloys are formed on SOI substrates havingan SOI layer of about 500 Å or less, the SiGe layers can remainsubstantially strained compared to identical SiGe layers formed onthicker SOI substrates and subsequently annealed and/or oxidized at hightemperatures. The present invention thus provides a method of‘frustrating’ metastable strained SiGe layers by growing them on thin,clean and high-quality SOI substrates.

The present method has applications to, for example, 1) the selectiverelaxation of SiGe on a given substrate surface or 2) having fullystrained SGOI with SiGe thickness greater than the critical value for agiven Ge fraction. In case 1) above, one can use a method of implantingions into the thin Si layer to create dislocations that allow relaxationto occur in regions in which the implantation is performed.

In broad terms, the method of the present invention, which is useful infabricating high-quality metastable SiGe-on-insulators, comprises thesteps of:

forming a Ge-containing layer on a surface of a top Si-containing layerhaving a thickness of about 500 Å or less and being located on a barrierlayer that is resistant to Ge diffusion; and

heating said layers at a temperature which permits interdiffusion of Gethroughout said top Si-containing layer and said Ge-containing layerthereby forming a substantially metastable, SiGe layer that is resistantto relaxation atop said barrier layer.

The metastable, strained single crystal layer SiGe layer formed usingthe method of the present invention can be a continuous layer that ispresent atop the entire substrate, or it can be present as a patternedregion atop the substrate.

The present invention also provides a SiGe-on-insulator substratematerial that is formed using the above-mentioned processing steps.Specifically, the inventive substrate material comprises a Si-containingsubstrate, an insulating region that is resistant to Ge diffusionpresent atop the Si-containing substrate, and a substantially metastableSiGe layer which is resistant to relaxation present atop the insulatingregion.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1D are pictorial representations (through cross-sectionalviews) showing the basic processing steps that are employed in thepresent invention in fabricating a high-quality, substantiallymetastable SiGe-on-insulator substrate material wherein the initialsubstrate includes an unpatterned diffusion barrier region.

FIGS. 2A-D are pictorial representations (through cross-sectional views)showing the basic processing steps that are employed in an alternativeembodiment of the present invention in fabricating a high-quality,substantially metastable SiGe-on-insulator substrate material whereinthe initial substrate includes a patterned diffusion barrier region.

FIGS. 3A-3B are pictorial representations (through cross-sectionalviews) showing an alternative embodiment of the present inventionwherein a Si cap layer is formed atop a Ge-containing layer which isformed on an unpatterned (3A) or patterned (3B) substrate.

FIGS. 4A-4B are pictorial representations (through cross-sectionalviews) showing an alternative embodiment of the present invention inwhich selective ion implantation is performed to form regions ofmetastable and strained SiGe and relaxed SiGe atop a barrier layer thatis resistant to Ge diffusion.

FIG. 5 is a graph plotting final SGOI Relaxation (%) vs. starting SOIthickness (Å).

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides a method of fabricatinghigh-quality, substantially metastable SiGe-on-insulator substratematerials in which the SiGe layer is resistant to relaxation, will nowbe described in greater detail by referring to the drawings theaccompany the present application. In the drawings, like and/orcorresponding elements are referred to by like reference numerals.

Reference is first made to FIG. 1A and FIG. 2A which show initialsubstrate materials that can be employed in the present invention.Specifically, the initial substrate materials illustrated in FIGS. 1Aand 2A each comprise Si-containing semiconductor substrate 10, barrierlayer 12 which is resistant to Ge diffusion (hereinafter “barrierlayer”) present atop a surface of Si-containing semiconductor substrate10 and a top Si-containing layer 14 present atop the barrier layer 12.The difference between the two initial structures depicted in thedrawings is that, in FIG. 1A, the barrier layer 12 is presentcontinuously throughout the entire structure, whereas in FIG. 2A, thebarrier layer 12 is present as discrete and isolated regions or islandsthat are surrounded by semiconductor material, i.e., layers 10 and 14.Note that the initial structure shown in FIG. 1A thus includes anunpatterned barrier layer, whereas the initial structure of FIG. 2Aincludes a patterned barrier layer.

Notwithstanding whether the barrier layer is patterned or unpatterned,the initial structure may be a conventional silicon-on-insulator (SOI)substrate material wherein region 12 is a buried oxide region whichelectrically isolates top Si-containing layer 14 from the Si-containingsubstrate semiconductor substrate 10. The top Si-containing layer 14 canbe referred to as the SOI layer. The term “Si-containing” as used hereindenotes a single crystal semiconductor material that includes at leastsilicon. Illustrative examples include, but are not limited to: Si,SiGe, SiC, SiGeC, Si/Si, Si/SiC, Si/SiGeC, and preformedsilicon-on-insulators which may include any number of buried oxide(continuous, non-continuous or mixtures of continuous andnon-continuous) regions present therein.

The SOI substrate may be formed utilizing conventional SIMOX (separationby ion implantation of oxygen) processes well-known to those skilled inthe art, as well as the various SIMOX processes mentioned in co-assignedU.S. patent application Ser. No. 09/861,593, filed May 21, 2001; Ser.No. 09/861,594, filed May 21, 2001; Ser. No. 09/861,590, filed May 21,2001; Ser. No. 09/861,596, filed May 21, 2001; and Ser. No. 09/884,670,filed Jun. 19, 2001 as well as U.S. Pat. No. 5,930,634 to Sadana, etal., the entire contents of each are being incorporated herein byreference. Note that the process disclosed in the '590 application canbe employed herein to fabricate the patterned substrate shown in FIG.2A. Alternatively, the SOI substrate material may be made using otherconventional processes including, for example, a thermal bonding andlayer transfer process.

In addition to SOI substrates, the initial substrates shown in FIGS. 1Aand 2A may be a non-SOI substrate that is made using conventionaldeposition processes as well as lithography and etching (employed whenfabricating a patterned substrate). Specifically, when non-SOIsubstrates are employed, the initial structure is formed by depositing acrystalline Ge diffusion barrier layer atop a surface of a Si-containingsubstrate, via conventional deposition, thermal growing processes oratomic layer deposition (ALD); optionally patterning the barrier layerby employing conventional lithography and etching; and thereafterforming a Si-containing layer atop the barrier layer using conventionaldeposition processes including chemical vapor deposition (CVD),plasma-assisted CVD, sputtering, evaporation, chemical solutiondeposition or epitaxial Si growth.

Barrier layer 12 of the initial structure shown in FIGS. 1A and 2Acomprises any insulating material that is highly resistant to Gediffusion. Examples of such insulating and Ge diffusion resistantmaterials include, but are not limited to: crystalline ornon-crystalline oxides or nitrides.

In accordance with the present invention, the top Si-containing layer 14of the initial structure is a relatively thin layer. The term“relatively thin” is used in the present invention to denote a topSi-containing layer 14 thickness of about 500 Å or less, with athickness of from about 10 to about 350 Å being more highly preferred.The thin top Si-containing layer 14 can be obtained by cutting, properchoice of implantation conditions, proper choice of depositionconditions, etching, planarization or oxidation-based thinning ofthicker SOI layers.

In the case of barrier layer 12 (i.e., Ge diffusion resistant layer),that layer may have a thickness of from about 1 to about 1000 nm, with athickness of from about 20 to about 200 nm being more highly preferred.The thickness of the Si-containing substrate layer, i.e., layer 10, isinconsequential to the present invention.

FIGS. 1B and 2B illustrate the structure that is formed afterGe-containing layer 16 is formed atop the top Si-containing layer 14.The Ge-containing layer 16 can be comprised of pure Ge or a SiGe alloylayer. The term “SiGe alloy layer” includes SiGe alloys that comprise upto 99.99 atomic percent Ge, more preferably alloys where the Ge contentis from about 0.1 to about 99.9 atomic percent. Even more preferably,the SiGe alloys used in the present invention have a Ge atomic percentof from about 10 to about 35.

In accordance with the present invention, the Ge-containing layer 16 isformed atop first Si-containing layer 14 using any conventionalepitaxial growth method that is known to those skilled in the art thatis capable of growing a SiGe alloy or pure Ge layer that is metastableand substantially free from defects, i.e., misfit and threadingdislocations. Illustrative examples of such epitaxial growing processesthat are capable of growing metastable and substantially defect freefilms include, but are not limited to: low-pressure chemical vapordeposition (LPCVD), ultra-high vacuum chemical vapor deposition(UHVCVD), atmospheric pressure chemical vapor deposition (APCVD),molecular beam (MBE) epitaxy and plasma-enhanced chemical vapordeposition (PECVD).

The thickness of the Ge-containing layer 16 formed at this point of thepresent invention may vary, but typically layer 16 has a thickness offrom about 10 to about 500 nm, with a thickness of from about 20 toabout 200 nm being more highly preferred.

In an alternative embodiment of the present invention, see FIGS. 3A-3B,optional cap layer 18 is formed atop the Ge-containing layer 16 prior toperforming the heating step of the present invention. The optional caplayer 18 employed in the present invention comprises any Si materialincluding, but not limited to: epitaxial silicon (epi-Si), amorphoussilicon (a:Si), single or polycrystalline Si or any combination thereofincluding multilayers. In a preferred embodiment, the cap layer iscomprised of epi Si. It is noted that layers 16 and 18 may, or may not,be formed in the same reaction chamber.

When present, the optional cap layer 18 has a thickness of from about 1to about 100 nm, with a thickness of from about 1 to about 30 nm beingmore highly preferred. The optional cap layer 18 is formed utilizing anyknown deposition process including the epitaxial growth processesmentioned above.

In one embodiment of the present invention, it is preferred to form apure Ge or SiGe alloy (15 to 20 atomic percent Ge) layer having athickness of from about 1 to about 500 nm on the surface of aSi-containing layer, and thereafter forming a Si cap layer having athickness of from about 1 to about 100 nm atop the Ge-containing layer.

After forming the Ge-containing layer 16 (and optional cap layer 18)atop the initial structure, the structure shown in either FIG. 1B, 2B,3A or 3B is then heated, i.e., annealed, at a temperature which permitsinterdiffusion of Ge throughout top Si-containing layer 14,Ge-containing layer 16 and, if present, the optional Si cap 18 therebyforming a substantially metastable, single crystal SiGe layer 20 that ishighly resistant to relaxation atop the barrier layer. During theheating step, a surface oxide layer 22 is formed atop the SiGe layer 20.The surface oxide layer 22 is typically, but not always, removed fromthe structure after the heating step using a conventional wet etchprocess wherein a chemical etchant such as HF that has a highselectivity for removing oxide as compared to SiGe is employed. FIGS. 1Cand 2C show the structure that is formed after the heating steps hasbeen performed.

Note that when the surface oxide layer 24 is removed, a single crystalSi layer can be formed atop layer 20 and the above processing steps ofthe present invention may be repeated any number of times to produce amultilayered substantially metastable SiGe substrate material.

The surface oxide layer 22 formed after the heating step of the presentinvention has a variable thickness which may range from about 10 toabout 1000 nm, with a thickness of from about 20 to about 500 nm beingmore highly preferred.

Specifically, the heating step of the present invention is an annealingstep that is performed at a temperature of from about 900° to about1350° C., with a temperature of from about 1200° to about 1335° C. beingmore highly preferred. Moreover, the heating step of the presentinvention is carried out in an oxidizing ambient which includes at leastone oxygen-containing gas such as O₂, NO, N₂O, ozone, air and other likeoxygen-containing gases. The oxygen-containing gas may be admixed witheach other (such as an admixture of O₂ and NO), or the gas may bediluted with an inert gas such as He, Ar, N₂, Xe, Kr, or Ne.

The heating step of the present invention may be carried out for avariable period of time that typically ranges from about 10 to about1800 minutes, with a time period of from about 60 to about 600 minutesbeing more highly preferred. The heating step may be carried out at asingle targeted temperature, or various ramp and soak cycles usingvarious ramp rates and soak times can be employed.

The heating step is performed under an oxidizing ambient to achieve thepresence of a surface oxide layer 22, which acts as a diffusion barrierto Ge atoms. Therefore, once the oxide layer is formed on the surface ofthe structure, Ge becomes trapped between barrier layer 12 and surfaceoxide layer 22. As the surface oxide increases in thickness, the Gebecomes more uniformly distributed throughout layers 14, 16, andoptionally 18, but it is continually and efficiently rejected from theencroaching oxide layer. So as the (now homogenized) layers are thinnedduring this heating step, the relative Ge fraction increases. Efficientthermal mixing is achieved in the present invention when the heatingstep is carried out at a temperature of from about 1200° to about 1320°C. in a diluted oxygen-containing gas.

It is also contemplated herein to use a tailored heat cycle that isbased upon the melting point of the SiGe layer. In such an instance, thetemperature is adjusted to tract at or near the melting point of theSiGe layer. This procedure is disclosed, for example, in co-pending andco-assigned U.S. patent application Ser. No. 10/448,948, filed May 30,2003. The content of the aforementioned U.S. application is incorporatedherein by reference.

If the oxidation occurs too rapidly, Ge cannot diffuse away from thesurface oxide/SiGe interface fast enough and is either transportedthrough the oxide (and lost) or the interfacial concentration of Gebecomes so high that the alloy melting temperature will be reached.

The role of the heating step of the present invention is to allow Geatoms to diffuse more quickly thereby maintaining a homogeneousdistribution during annealing. After this heating step has beenperformed, the structure includes a uniform and substantially metastableSiGe alloy layer 20, sandwiched between barrier layer 12 and surfaceoxide layer 22. Because the initial Si-containing layer was thin, thethus formed SiGe alloy layer is frustrated since it is not permitted torelax because the usual mechanisms responsible for nucleation and growthof strain-relieving dislocations have, in some way, changed. Themeasured relaxation of the substantially metastable SiGe layer isbetween 0 to 85% of the relaxation value measured on similar SiGe layersformed using thicker starting SOI layers (greater than 500 Å). Moretypically, the measured value of relaxation is between 5 to 50% of thevalue that is measured on equivalent SiGe layers formed using thickerstarting SOI layers; the resistance to relaxation is a function of theSOI thickness as shown in FIG. 5.

In accordance with the present invention, the SiGe layer 20 has athickness of about 2000 nm or less, with a thickness of from about 10 toabout 100 nm being more highly preferred. Note that the SiGe layer 20formed in the present invention is thin.

The SiGe layer 20 formed in the present invention has a final Ge contentof from about 0.1 to about 99.9 atomic percent, with an atomic percentof Ge of from about 10 to about 35 being more highly preferred. Anothercharacteristic feature of SiGe layer 20 is that it is a strained layer.

As stated above, the surface oxide layer 22 may be stripped at thispoint of the present invention so as to provide the SiGe-on-insulatorsubstrate material shown, for example, in FIGS. 1D or 2D (note that thesubstrate material does not include the cap layer since that layer hasbeen used in forming the SiGe layer).

In some embodiments of the present invention, it is possible to form asubstrate material wherein portions of the SiGe layer are substantiallyrelaxed and other portions of the SiGe layer are substantiallymetastable and strained. Such an embodiment is depicted in FIGS. 4A-4B.In this embodiment, ions are implanted into predetermined portions ofthe top Si-containing layer 14 prior to annealing. Specifically afterforming the Ge-containing layer 16 (with or without the optional caplayer 18) atop the initial structure, the structure is then subjected toan ion implantation step wherein ions that are capable of forming ornucleating strain-relieving defects within the top Si-containing layer14 or near the interface between the top Si-containing layer 14 and theGe-containing layer 16 is performed. Almost any ions can be used to formor nucleate strain-relieving defects because dislocations can nucleatefrom a wide range of crystalline imperfections such as vacancy clusters,point defects, platelet defects and bubble or void defects. The implantmay be performed with an implantation mask that is located on thesurface of the structure or some distance from the structure.

The structure after this implantation step is shown in FIG. 4A (withoutoptional cap layer). In this figure, reference numeral 19 denotes thedefect regions formed by the ion implantation step and reference numeral17 denotes the interface between the top Si-containing layer 14 and theGe-containing layer 16. The defect regions solve the problem of defectproduction in the Ge-containing layer/Si-containing layer bilayer byallowing formation or nucleation and growth of strain-relieving defectsin said regions.

Implantation conditions for a particular ion are chosen to place the ionpeak concentration within or near the Si-containing layer 14. Highlypreferred ions are those that are compatible with modern CMOSmanufacturing: H, B, C, N, O, Si, P, Ge, As or any of the inert gasions. Example ions used in the present invention are hydrogen ions (H⁺).It is noted that other species of hydrogen such as H₂ ⁺ are alsocontemplated herein.

The implant step of the present invention is conducted at approximatelyroom temperature, i.e., a temperature of from about 283 K to about 303K, using a beam current density of from about 0.01 to about 10microamps/cm². Implantation at different temperatures and/or using otherbeam current densities may affect defect formation.

The concentration of the implant species used in forming the plateletdefects may vary depending upon the type of implant species employed.Typically, however, the concentration of implanted ions (H) used at thispoint of the present invention is below 3E16 cm⁻², with an ionconcentration of from about 1E16 to about 2.99E16 cm⁻² being more highlypreferred. The energy of this implant may also vary depending upon thetype of ion that is being implanted, with the proviso that the implantenergy must be capable of positioning ions within layer 14 or near theinterface between layers 14 and 16. For example, when hydrogen isemployed as the implant ion, the energy used to ensure defect formationwithin layer 14 or near the interface between layers 14 and 16 is fromabout 1 to about 100 keV, with an energy of from about 3 to about 20 keVbeing more highly preferred.

After the implant step, and if not previously formed on the structure,the optional cap may be formed atop the Ge-containing alloy layer. Next,the implanted structure is heated, i.e., annealed, using the conditionsdescribed above. FIG. 4B illustrates the structure that is formed afterthe annealing step. In this drawing, the surface oxide layer has beenremoved. The substantially metastable and strained SiGe portions arelabeled as 20, while substantially relaxed SiGe portions that receivedthe above described ion implant are labeled as 23. The measuredrelaxation of the substantially relaxed SiGe region 23 is between 90 to110% of the relaxation value measured on SiGe layers with equivalentfilm thickness and Ge concentration formed using thicker starting SOIlayer 14 (greater than 500 Å) without ion implantation. The possibilityof relaxed SiGe region 23 having greater than 100% of the relaxationvalue of equivalent SiGe layers is due to the fact that ion-implantedstrained layers tend to relax more efficiently because of the randomnature of the defect nucleation.

A Si layer can be formed atop the SiGe layer (relaxed and/or metastable)using a conventional epitaxial deposition process well-known in the art.The thickness of the epi-Si layer may vary, but typically, the epi-Silayer has a thickness of from about 1 to about 100 nm, with a thicknessof from about 1 to about 50 nm being more highly preferred.

In some instances, additional SiGe can be formed atop SiGe layer(relaxed and/or metastable) utilizing the above-mentioned processingsteps, and thereafter an epi-Si layer may be formed. Because the relaxedSiGe layer has a large in-plane lattice parameter as compared to theepi-Si layer, the epi-layer will be strained in a tensile manner.

As stated above, the present invention also contemplates superlatticestructures as well as lattice mismatched structures which include atleast the SiGe-on-insulator substrate material of the present invention.In the case of superlattice structures, such structures would include atleast the SiGe-on-insulator substrate material of the present invention,and alternating layers Si and SiGe formed atop the SiGe layer of thesubstrate material.

In the case of lattice mismatched structures, GaAs, GaP or other likecompound would be formed atop the SiGe layer of the inventiveSiGe-on-insulator substrate material.

The following example is provided to illustrate the method of thepresent ion as well as some advantages that may be obtained therefrom.

EXAMPLE

In this example, the final SGOI relaxation for samples having variousSOI starting thickness were determined. Specifically, the measuredrelaxation of SGOI layers made by growing 600 Å-17% SiGe on SOIsubstrates with a top SOI layer having a thickness ranging from 1450 Ådown to 200 Å was determined. All of the structures were then convertedinto approximately 380 Å-28% SiGe SGOI using the method described above.Specifically, the initial SiGe/Si bilayer is oxidized at a hightemperature of about 1200° C. allowing Ge to diffuse uniformlythroughout the layers while being rejected from the growing surfaceoxide layer. This way, the total Ge content is retained as the(homogenized) SGOI layer is thinned by the oxidation process. The SOIthickness reported in FIG. 5 does not take into account the thin Sibuffer layer that is grown before the SiGe layer is grown which is partof the low-temperature epitaxial process. FIG. 5 clearly shows a rapiddecrease in the measured relaxation (using X-ray diffraction) of thefinal SGOI with decreasing initial top SOI layer thickness. It is theregion in FIG. 5 below 500 Å starting SOI thickness that the inventivehighly metastable and relaxation-resistantsilicon-germanium-on-insulator is realized.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the scope and spirit ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1-24. (canceled)
 25. A substrate material comprising: a Si-containingsubstrate; an insulating region that is resistant to Ge diffusionpresent atop the Si-containing substrate; and a substantially metastableSiGe layer which is resistant to relaxation present atop the insulatingregion.
 26. The substrate material of claim 25 wherein said insulatingregion is patterned.
 27. The substrate material of claim 25 wherein saidinsulating region is unpatterned.
 28. The substrate material of claim 25wherein said insulating region comprises crystalline or non-crystallineoxides, or crystalline or non-crystalline nitrides.
 29. The substratematerial of claim 25 wherein said insulating region is a buried oxideregion that is patterned or unpatterned.
 30. A substrate materialcomprising: a Si-containing substrate; an insulating region that isresistant to Ge diffusion present atop the Si-containing substrate; anda substantially metastable SiGe region which is resistant to relaxationpresent atop the insulating region; and a relaxed SiGe region abuttingthe substantially metastable SiGe region.